Design and Testability Explorer

☐

n.a.

✓

Import Netlsts, assign device models and classify component types, browse UUT features

Browse Unit Under Test design data (netlist information, etc.) in various list views and other representations; also provides the means to classify component types and to link the CAD data to device libraries assigned to the project; Net Browsing tools in SYSTEM CASCON (NetList Navigator, NetList Explorer) provide quick and easy access to all nets on the Unit Under Test as well as to all pins connected to these nets and their properties. Color coding allows quick visual differentiation between nets of certain types, such as test bus nets vs. Boundary Scan nets vs. Power and Ground nets, and so on.

DfT Design Rule Checker

☐

200-217

option

Automatic rule checker for JTAG/BScan designs

Netlist Merger

☐

200-201

option

✓

Automatically merge netlist for multiple boards or nets of the same board;

The Net List Merger can be used to merge multiple net lists to obtain a system net list, which is used to
generate test programs for a specific system configuration. Furthermore, nets within the same net list file can be merged with this tool, accommodating test programs incorporating loopback connectors.
Multiple merging steps can be created to accommodate various system configurations. The net merging tool allows a user to easily create test applications for system configurations. Such system configurations could consist or a mother board that carries one or more daughter cards, or a backplane based system with one or multiple cards plugged into backplane slots, supporting interconnect tests between those daughter cards or between plug-in cards in various system slots.

Test Coverage Analyzer

☐

200-202

option

✓

Automatic fault coverage calculation at net and pin level

Generates an overall test coverage report based on the actual test programs; considers ALL nets on the Unit Under Test and provides details about tested and not tested (or not fully tested) pins and nets; the resulting report file contains lists detailing pin and net oriented test coverage and provides statistics at pin, device, and net level; the contents of the Test Coverage Report file can be customized. It can be generated for an individual test or for a batch of test programs.

ScanVision III Layout Reader

☐

200-308

option

Layout data importer (specify CAD system when ordering)

ScanVision III Schematic Reader

☐

200-309

option

Schematic data importer (specify PDF or EDA system when ordering)

ScanVision III Layout Visualizer

☐

200-310

option

Interactive Layout Visualizer (based on layout database created by ScanVision III Layout Reader)

ScanVision III Schematic Visualizer

☐

200-311

option

Interactive Schematic Visualizer (based on schematic database created by ScanVision III Layout Reader)

ScanVision III Virtual Schematic

☐

200-312

option

Interactive Synthetic Schematic Visualizer (does not require any ScanVision III import)

Advanced Vector Browser

☐

n.a.

✓

Table representation of test vectors with highlighted faults

For Go/No-Go test applications generated automatically, or for manually written tests, or even for tests that include diagnostic messages, the Advanced Vector Browser provides an inside look at the actual test pattern applied to the Unit Under Test. Mismatches between expected and measured pattern are highlighted in red.

ScanAssist Multi-Mode Debugger

☐

200-216

option

✓

Interpretive debugger, waveform tracing, register watching, breakpoint definition, Interactive Command executor

Interpretive debugger; provides various ways to observe any Boundary Scan resources on the UUT and to
interact with the test application, even to modify existing or to add additional test steps;
waveform tracing, register watching, breakpoint definition, Interactive Command executor, and more;
interfaces with Design Explorer and with ScanVision tools (if available)

ScanAssist Interactive Pin Toggler

☐

200-313

option

✓

Interactive Pin and Net Toggler

Interactive Pin and Net Toggler, Constraints and Vector Safety Checker, CASLAN Recorder, Logic Cluster Simulator; interfaces with Design Explorer and with ScanVision tools (if available); Best-In-Test 2008 award winner (T&MW)

Manual Interlaced Emulation Test Generation (VarioTAP)

☐

200-400

option

✓

JTAG Emulation (VarioTAP) based manual functional test program generation (VarioTAP Model needed), combining Boundary Scan with Emulation

ATPG Simulation Vectors (DTIF)

☐

200-314

option

Automatic test program generation based on DTIF (IEEE1445), incl. Reader and support for (dynamic) functional test (special h/w needed)

ATPG Flying (Guided) Probe

☐

200-214

option

Automatic Test Program Generation for any Prober

Automatically generate continuity test for Boundary Scan interconnections with utilization of Flying Probes to extend test coverage and testability; Includes test of presence of serial and pull-up/-down resistors; Includes test of transparent logic; Provides testability report

ATPG Logic Components Test

☐

200-300

option

✓

Automatic Test Program Generation for logic IC clusters

Automatically generate structural test for Logic Component Clusters (e.g. NAND, OR, etc.); Based on functional model description in device library; Provides testability report

ATPG Memory Access Test

☐

200-204

option

✓

Automatic Test Program Generation for Memory device clusters

The Memory Access Test verifies connections between a Boundary Scan device and a memory device (such as an SRAM, DRAM, SDRAM, DDR SDRAM, etc.), including buffers or glue logic embedded between the two. Even though the Interconnect Test typically already tests the address, data, and control bus for shorts, the memory access test checks for open pins on the respective signal paths. The test is based on functional access cycles to the memory, applied through Boundary Scan I/O pins. The functional access cycles are part of the memory device models in the CASCON Device Library. Just like in any other application in SYSTEM CASCON, Scan Router devices are handled automatically.

ATPG Cluster Table Test

☐

200-203

option

✓

Automatic Test Program Generation for non-BScan clusters based on truth-table

Automatically generate structural test for logic clusters; Based on cluster table (stimulus and expected pattern); Provides testability report (.CNP); Based on a Cluster Table describing the actual test pattern, the Device Cluster Test verifies the basic functionality of (and connectivity within) a logic cluster or other non-Boundary Scan circuitry that can be stimulated and observed with Boundary Scan I/O pins. Scan Router devices are handled automatically.

ATPG Interconnect Test IEEE 1149.6

☐

200-302

option

✓

Automatic Test Program Generation for connectivity test of IEEE 1149.6 I/O

Automatically generate continuity test for IEEE 1149.6 compliant Boundary Scan interconnections (such as
AC-coupled networks that are accessible with IEEE 1149.6 compliant test resources);

ATPG Interconnect Test IEEE 1149.1

☐

200-212

option

✓

Automatic Test Program Generation for connectivity test of IEEE 1149.1 I/O

Automatically generate continuity test for IEEE 1149.1 compliant Boundary Scan interconnections; Includes test of presence of serial and pull-up/-down resistors; Includes test of transparent logic; Provides testability report; The Interconnect Test checks the Unit Under Test for structural faults on I/O pins introduced during the
manufacturing process, such as open pins, stuck-at-1/0 pins, and shorted nets. This test includes not only Boundary Scan I/O pins, but also transparent components between two Boundary Scan pins, such as serial resistors, logic gates, and buffers/transceivers. Even pull-up and pull-down resistors can be checked for
presence in many cases. The Interconnect Test in SYSTEM CASCON supports both IEEE 1149.1 and IEEE 1149.6 compliant devices. Scan Router devices are handled automatically.

ATPG Infrastructure Test

☐

n.a.

✓

Automatic Test Program Generation for JTAG/BScan infrastructure; Verify Scan Chain integrity, Device ID Codes, register lengths and capture values

Automatically generate integrity test for Boundary Scan infrastructure; Includes testing of test bus connections, register lengths and capture values for ID-Code, User-Code, Bypass, Instruction and Boundary Scan Registers; Scan Router devices are handled automatically.

Universal Manual Test Development

☐

n.a.

✓

Manual Test Program Generation in CASLAN language

Any Boundary Scan test can also be written manually in SYSTEM CASCON™/POLARIS™ proprietary programming language CASLAN; CASLAN is similar to PASCAL+Assembly; High-level commands; Also, every ATPG test is written in CASLAN

Test Generation for IEEE 1149.4

☐

n.a.

✓

Test Program Generation for IEEE 1149.4 resources

Manual test program development for analog/mixed-signal Boundary Scan tests (utilizing IEEE 1149.4
compliant test resources), in CASLAN language;

Automated FLASH ISP (AFPG)

☐

284-100

option

✓

Automatic FLASH program generator (incl. Manual Flash ISP)

Automatically find BScan pins controlling the FLASH component; Re-assign test resources (e.g. PIP); Based on functional description in device library; May include buffer and glue logic; Select actions, data files, etc. in GUI; Scan Router devices are handled automatically; programming data can be provided in Intel HEX files, Motorola S-Record files, and in binary image files (the actual programming file can be fixed as part of the programming routine, or can be selected by the operator at run-time);

Manual FLASH ISP

☐

284-110

option

✓

Manual FLASH program generation (CASLAN language)

Enables basic FLASH programming features; Manually create a CASLAN program assigning BScan pins or PIP channels to control the FLASH component; Based on functional description in device library;

OnChip FLASH ISP (VarioTAP)

☐

284-120

option

✓

JTAG Emulation (VarioTAP) based Program Generator for On-Chip Flash and µP connected external Flash (VarioTAP Model needed)

PLD Program Generators

☐

285-100

option

✓

PLD program generators for SVF, JAM/STAPL, IEEE 1532

Supports SVF, JAM, STAPL, XSVF, and IEEE 1532 for device programming; Programming files typically
provided by PLD vendor software; Scan Router devices are handled automatically;

Data Import Processors

☐

n.a.

✓

Supporting Intel-Hex, Motorola S-Record, binary data files; SVF, STAPL, TDS;

Test programs and PLD In-System Programming (ISP) routines in file formats such as Standard Test And Programming Language (STAPL, Jedec Standard 71) and Serial Vector Format (SVF) can be imported into
SYSTEM CASCON.

Data Export Processors (option for SX versions)

☐

200-391

✓

Export of test and ISP routines in SVF, STAPL, TDS formats

In addition to the SYSTEM CASCON native test formats, test programs and PLD In-System Programming (ISP) routines can be exported in file formats such as Standard Test And Programming Language (STAPL, Jedec Standard 71) and Serial Vector Format (SVF).

PFD Simulation Vectors (DTIF)

☐

200-315

option

Pin Fault Diagnostics based on Fault Dictionary of imported DTIF

PFD Flying (Guided) Probe

☐

200-215

option

Pin Fault Diagnostics for Flying (Guided) Probe ATPG

PFD Logic Components Test

☐

200-301

option

✓

option

✓

Pin Fault Diagnostics for logic IC cluster

PFD Memory Access Test

☐

200-206

option

✓

option

✓

Pin Fault Diagnostics for Memory ATPG

PFD Cluster Table Test

☐

200-205

option

✓

option

✓

Pin Fault / Net level Diagnostics for Cluster ATPG

PFD Interconnection 1149.1/1149.6

☐

200-213

option

✓

option

✓

Pin Fault Diagnostics for IEEE1149.1 and IEEE1149.6

PFD Infrastructure Test

☐

n.a.

✓

Diagnostics for Infrastructure Test

Universal Pin Failure Detection

☐

n.a.

✓

Diagnostic support for manually written test programs

Diagnostic support for manually created test programs and for Go/No-go tests; extend of messages written into test result file can be configured for each test;

Failure Diagnostics 1149.4

☐

n.a.

✓

Diagnostic support for 1149.4 tests

Diagnostic support for manually created test programs exercising IEEE 1149.4 compliant test resources for analog/mixed-signal Boundary Scan tests

VTM-Flash ISP/ARM7

☐

VTF-001

option

VarioTAP Execution model for Flash programming (On Chip and external) for µP with ARM7 core from ARM

VTM-Flash ISP/ARM9

☐

VTF-002

option

VarioTAP Execution model for Flash programming (On Chip and external) for µP with ARM9 core from ARM

VTM-Flash ISP/ARM11

☐

VTF-003

option

VarioTAP Execution model for Flash programming (On Chip and external) for µP with ARM11 core from ARM

VTM-Flash ISP/Xscale

☐

VTF-004

option

VarioTAP Execution model for Flash programming (On Chip and external) for Intel/Marvell µP (PXAxxx) with ARM core from ARM

VTM-Flash ISP/Cortex

☐

VTF-005

option

VarioTAP Execution model for Flash programming (On Chip and external) for µP with Cortex core from ARM

VTM-Flash ISP/Renesas H8S21xx

☐

VTM-006

option

VarioTAP Execution model for Flash programming (On Chip and external) for Renesas H8S21xx µP

VTM-Flash ISP/TI TMS320Fxxx

☐

VTM-007

option

VarioTAP Execution model for Flash programming (On Chip and external) for TI TMS320Fxxx DSP

VTM-Bus Test/ARM7

☐

VTB-001

option

VarioTAP Execution model for Bus Test for µP with ARM7 core (ARM), incl. Test control for Bus Devices, Interlaced JTAG Bscan Test and execution of user coded standard test routines

VTM-Bus Test/ARM9

☐

VTB-002

option

VarioTAP Execution model for Bus Test for µP with ARM9 core (ARM), incl. Test control for Bus Devices, Interlaced JTAG Bscan Test and execution of user coded standard test routines

VTM-Bus Test/ARM11

☐

VTB-003

option

VarioTAP Execution model for Bus Test for µP with ARM11 core (ARM), incl. Test control for Bus Devices, Interlaced JTAG Bscan Test and execution of user coded standard test routines

VTM-Bus Test/Xscale

☐

VTB-004

option

VarioTAP Execution model for Bus Test for Intel/Marvell PXAxxx, Xscale, incl. Test control for Bus Devices, Interlaced JTAG Bscan Test and execution of user coded standard test routines

VTM-Bus Test/Cortex

☐

VTB-005

option

VarioTAP Execution model for Bus Test for µP with Cortex core (ARM), incl. Test control for Bus Devices, Interlaced JTAG Bscan Test and execution of user coded standard test routines

VTM-Bus Test/<type>

☐

VTS-xxx

option

VarioTAP Execution model for System Emulation Test for the < type of µP>, incl. All Test control functions for On-Chip Periphery, all Bus Emulation Test functions and all Flash ISP functions

Test/ISP (Batch) Execution

☐

n.a.

✓

The test and in-system programming (ISP) applications can be executed individually or as part of a batch
sequence. Such applications can be run once or continuously. Test results are presented on screen and are also written into a test result file. In case of faults, automatically generated test programs provide detailed
diagnostic messages in plain English.
In SYSTEM CASCON, any test or ISP application checks the scan chain integrity every time test or programming data is shifted through the chain, therefore ensuring that a broken scan chain does not cause pseudo error messages or unnecessarily long execution times. If necessary, this feature can be turned off at any time in a test or ISP application.
The test result file can contain additional information, such as date and time stamps, the UUT serial number, and additional comments.
Test and batch sequences can also call external executables.

Upgrade of TAP Limit (option for SX versions)

☐

200-392

✓

VarioCore Handler

☐

n.a.

✓

Enables dynamic reconfiguration of the functionality of individual or multiple SCANFLEX I/O modules based on special Intellectual Property (IP);

Hybrid Vector Splitter (HyScan)

☐

n.a.

✓

Enables simultaneous handling of parallel I/O pattern and serial scan pattern;

Scan Router Handler (option for SX versions)

☐

200-393

✓

Automated handling of Scan Router devices (such as TI ASP, Scan Path Linker, NSC Scan Bridge,
and Firecron Gateway, for example) in all test and ISP applications; supporting system level scan chain
infrastructures (including multi-drop configurations)

Gang Handler (option for SX versions)

☐

200-394

✓

Multiple UUTs of the same type can be tested and programmed in parallel in order to increase throughput.

CASCON Device Library

☐

✓

including BSDL import and export, STIL import; models for BScan and non-BScan devices including functional descriptions

CASCON Full Platform License

☐

n.a.

✓

CASCON API (CAPI)

☐

n.a.

✓

Multi-User Manager (myCASCON)

☐

n.a.

✓

SYSTEM CASCON includes multi-user management, supporting user specific options, access permissions, and login/password settings

Floating License Module Manager

☐

n.a.

[✓]

Floating License Seat

☐

200-220

[✓]

one included, additional as option

for flexLM based Floating License arrangement; single add-on seat for Floating License Access

Automated Process Scripting

☐

n.a.

[✓]

Automates various test development processes (such as test generation, compilation, etc.) once the required settings are made;

Software Maintenance Contract (SMC)

☐

200-101

[✓]

annual fee; percentage of software license price

Annual s/w support contract, mandatory for the first year. Incl. GENESIS access, s/w update / upgrade via web, library refresh via web, first priority for bug fixing, email support, hot line support

Software License Upgrade (SLU)

☐

200-102

[✓]

monthly fee as percentage of software license price, times number of months since expiration of SMC

Update fee for software license with expired Software Maintenance Contract (SMC) to latest software release