Complex FPGA devices typically provide banks of I/O pins that can be configured for a certain logic family (voltage levels and other I/O parameters are programmable/configurable per I/O banks). Typically such devices has reference voltage pins per I/O bank. When the FPGA is not configured, the I/O banks default to a preset logic family, e.g. LVTTL.

On a Printed Circuit Assembly (PCA) such an FPGA is connected to other devices, some of which may require signal levels other than LVTTL. An common example are DDR2 or DDR3 devices. If a DDR2 device is connected directly to the FPGA device, for example, and the DDR2 device requires 1.8V or 2.5V signal levels as opposed to the default 3.3V levels provided by the FPGA device, it is necessary to configure the FPGA prior to running any memory cluster tests (write and read routines to that DDR2 memory). As a minimum, the I/O bank(s) connected to the DDR2 need to be configured for the proper signal leveling (so that the FPGA I/O pin signals match the DDR2 memory signal level requirements).

This configuration of the FPGA most likely will require a modification of the standard BSDL file for that device (which typically defines all I/O pins as bi-directional): if any of the FPGA I/O pins change their function (e.g. from bi-directional to input only or to output only) as a result of the device configuration, that change needs to be communicated to the test generation tools that create the test vectors to be applied to the Boundary Scan register of the FPGA, and hence to the memory device.  FPGA vendors typically offer tools to create such post-configuration BSDL files.