Also referred to as IJTAG (Internal JTAG), the IEEE P1687 working group intends to develop a methodology for access to embedded test and debug features (but not the features themselves) via the IEEE 1149.1 Test Access Port (TAP) and additional signals that may be required.
The IEEE 1149.1 standard specifies circuits to be embedded within a Integrated Circuit to support board test, namely the Test Access Port (TAP), TAP Controller, and a number of internal registers. In practice, the TAP and TAP controller are being used for other functions well beyond boundary scan in an ad-hoc manner across the industry to access a wide variety of internal chip test and debug features. The purpose of the IJTAG initiative is to provide an extension to the IEEE 1149.1 standard specifically aimed at using the TAP to manage the configuration, operation and collection of data from embedded test and debug circuitry. There exists the widespread use of embedded instrumentation (such as BIST Engines, Complex I/O Characterization and Calibration, Embedded Timing Instrumentation, etc.) each of which is accessed and managed by a variety of external instrumentation using a variety of mechanisms and protocols. Therefore, there exists a need for a standardization of these protocols in order to ensure an efficient and orderly methodology for the preparation of tests and the access and control of these embedded instruments.The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features.
(excerpt from the IEEE P1687 PAR application)
