Today, IEEE 1149.1 test resources are implemented in many digital circuits (such as CPU’s, DSP’s, PLD/FPGA’s, interface devices, etc.). Even some memory components (e.g. some SRAM and FIFO components) have Boundary Scan implemented, although some of them do not support the EXTEST capability as defined in IEEE 1149.1. However, many Memory components do not have any test resources built in.
The connectivity between Boundary Scan compliant components and such memory devices can only be tested by means of cluster testing (writing to the memory and reading back pattern written to the memory). This requires full access to the memory control pins, though. Many SDRAM or newer synchronous memory architectures are implemented on board level with clock circuitry that cannot be synchronized with Boundary Scan. That means that these memory structures cannot be tested via Boundary Scan in cluster tests. Today, no standard test methodology for memory testing is available. One approach introduced in the late 1990’s was SCITT. An IEEE working group (P1581) has been formed to create a standard test methodology for memory interconnect testing. In principle, P1581 describes test circuitry to be implemented in a memory device that bypasses the memory block itself and instead provides a logic connection between input and output pins (using simple logic gates). By stimulating the memory input pins and observing its output pins via BScan devices connected to the memory, board level connectivity can be verified; simplifying and accelerating this kind of test dramatically.
