DFT Guide

Boundary Scan test based on IEEE 1149.1 is well established today. However, in recent years new challanges have arrived the limit the test coverage achievable with traditional Boundary Scan testing. In order to provide solutions to test problems related with analog and mixed signal circuitry, differential signaling, and AC coupled networks new standards have been developed as part of the IEEE 1149.x family of test standards (IEEE 1149.4 and IEEE 1149.6, respectively). 

JTAG/Boundary Scan has been very successful in the past years and is widely adopted throughout the electroncis incustry. The test access port defined in IEEE 1149.1 enables device, board, and system level test applications, debug and emulation access, and even in-system programming. Still, there is room for improvement in some areas, such as cluster testing, access to embedded instruments from various IP vendors, test of multi-core devices and system-on-chip, and so on. New developments are under way to standardize the test of static interconnects (IEEE P1581), the access to device internal instrumentation, such as emulation, debug, and other instruments embedded in chips (IEEE P1687), and the definition of a compact JTAG interface (IEEE P1149.7).

A JTAG/Boundary Scan tutorial can be downloaded here.