Having addressable scan router devices (such as TI’s ASP [SN74ABT8996], National Semiconductor’s SCANBridge [SCANSTA111, SCANSTA112], or Firecron’s Gateway [JTS Gateway devices]) designed in at board level, supports the execution of device and board tests at system level.
Connections from one board to another board in a system through the backplane can be tested automatically, if the ATE tools support respective test pattern generation. Device and board level test in a system environment simplifies fault isolation and failure diagnostics in system assembly and field test.
System level test bus structures allow access to PLD and FLASH devices for the purpose of In-System Programming, thus allowing to easily reconfigure devices (e.g. upgrade firmware) in field.
There are other system level test applications that could benefit from system level JTAG access. The SJTAG working group is discussing such use cases.
If BScan device families with different voltage levels are used in a system scan chain, make sure to implement level shifting capabilities (e.g. via pull resistors or integrated level shifters).
Make test bus signals available on backplane connector (if existent).
