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Home DFT Guidelines Chip Level DFT Custom implementations and special features
DFT Guidelines for Semiconductor Devices

Custom implementations and special features

Sunday, 10 August 2008 20:18
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To accelerate FLASH programming procedures or other memory operations by Boundary Scan, the pulse generation for respective control signals could be generated internally in conjunction with BST (Boundary Scan Test) logic and/or outputs could be tri-state to apply control lines externally. Consider implementing special registers (including only the cells needed for a specific test application) in ASIC’s, so that scan cells not needed don’t lengthen the scan chain without providing any value for the test.
 

GOEPEL electronic’s TESSY extended is a fully automated electronic functional test system for the production of electronic devices in vehicles. TESSY extended supports EOL tester lines (EOL = End of Line) with cross-linked test cells, from Ident-Scan of the 2-D code via multiple parallel test to laser marking and sorting of faulty parts – for quantities of more than one million devices.  
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