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Home DFT Guidelines Chip Level DFT Optional features of IEEE 1149.1 compliant devices
DFT Guidelines for Semiconductor Devices

Optional features of IEEE 1149.1 compliant devices

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In addition to mandatory features, the IEEE Std. 1149.1 also specifies optional capabilities and resources. 
Optional device features include the following:
  • An IEEE-1149.1 compliant device may provide the optional Test Logic Reset pin (/TRST, low-active);
  • An IEEE-1149.1 compliant device may feature additional data registers (such as Identification Register, internal self test registers, etc.) and test instructions (such as IDCODE, HIGHZ, CLAMP, RUNBIST, etc.);
  • Private instructions may be implemented in a device, their opcode has to be identified in the components BSDL file;
  • Having an ID register designed in is extremely helpful throughout the whole product life cycle.
  • Built-In Self Test (BIST) is a very helpful feature especially for testing in production and field service.
  • The HIGHZ instruction can be used to tri-state all Boundary Scan outputs (including Output2) while the Bypass register is put between TDI and TDO of the component.
  • The CLAMP instruction should be supported because it allows the shortening of the scan path length without loss of external driven test values.
 

During National Electronics Week (NEW), GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions compliant with IEEE Std 1149.x, introduced CION Module™ /PCIe-x(1/4) as additional interface cards within the popular CION Module product range.
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