Some JTAG/Boundary Scan applications require only a small number of test vectors and therefore don't put any particular requirement on the performance/throughput of the JTAG test bus. Other applications, such as in-system programming of FLASH devices, though, rely on many thousands or even millions of shift vectors. For such applications, the test bus throughput has a very big impact on overall test execution times.
TCK frequency
- TCK frequency becomes important for memory cluster test, FLASH programming and other applications requiring a large number of scan cycles. For such applications try to structure the scan chains so that faster devices and slower devices are separated (only useful, if the slower devices are not needed for the application of the scan pattern for those particular tests).
- Transitions inside the TAP Controller State Machine happen on rising and falling edge of TCK. It is important to provide a TCK signal free of reflections or other parasitic effects causing in-continuity in the edges, especially around the TCK receiver threshold (edges need to be monotonic). Avoid glitches especially in the TCK signal.
Scan Chain Length
- Scan chain length becomes important for memory cluster test, FLASH programming and other data extensive applications.
- Consider implementing special registers (including only the cells needed for a specific test application) in ASIC’s, so that scan cells not needed don’t lengthen the scan chain without providing any value for the test. Such a special register could combine BScan cells used to control address, data and control bus signals used to program FLASH components, for example.
- Consider structuring the scan chains and board functions so that most devices can be kept in HIGHZ, CLAMP, or BYPASS, during scan cycle extensive applications.
