DFT Guidelines for JTAG/Boundary Scan

FPGA driven Memory Access Tests

Tuesday, 13 July 2010 22:51 Heiko Ehrenberg

Complex FPGA devices typically provide banks of I/O pins that can be configured for a certain logic family (voltage levels and other I/O parameters are programmable/configurable per I/O banks). Typically such devices has reference voltage pins per I/O bank. When the FPGA is not configured, the I/O banks default to a preset logic family, e.g. LVTTL.

Last Updated ( Tuesday, 13 July 2010 22:58 ) Read more...

IEEE 1149.4 Update

Thursday, 07 August 2008 20:15 Heiko Ehrenberg

Analog or Mixed signal circuitry is left out by IEEE 1149.1. Recognizing this shortcoming, an IEEE working group was formed in the early 1990s with the purpose to develop a standardized test access methodology for analog and mixed signal pins. In 1999 the effort resulted in the approval of the IEEE Std. 1149.4 (Standard for a Mixed Signal Test Bus). The purpose of this standard is to provide the means to measure and characterize device level or board level mixed-signal and analogue parameters.

In March 2011, the 2010 revision of IEEE Std 1149.4 was published, which provides a Boundary Scan Description Language (BSDL) extension for IEEE 1149.4, allowing software tools to utilize these files for automated test program generation.

Last Updated ( Wednesday, 20 April 2011 12:03 ) Read more...

New Boundary Scan I/O Modules enable structural Test of PCI Express Slots via IEEE Std. 1149.6

Sunday, 15 June 2008 19:09 Heiko Ehrenberg

During National Electronics Week (NEW), GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions compliant with IEEE Std 1149.x, introduced CION Module™ /PCIe-x(1/4) as additional interface cards within the popular CION Module product range.

IEEE 1149.1 Introduction

Thursday, 07 August 2008 20:13 Heiko Ehrenberg

The effort to develop a standardized test method that can solve test access problems caused by ever denser printed circuit designs, shrinking device geometries and new device packaging (such as BGA and CSP) started in the mid 1980s, when a group of European companies and institutions formed the Joint European Test Action Group (JETAG), which later changed its name to Joint Test Action Group (JTAG) when North American organizations joined the group.

Last Updated ( Sunday, 24 August 2008 16:58 ) Read more...

One chain. Or two? Or more?

Saturday, 02 August 2008 21:43 Heiko Ehrenberg

Often times it is recommended to combine all devices on a board to one Boundary Scan chain. However, there are applications where it is beneficial, if not even required, to split up the devices into two or more chains.

DFT Guide

FPGA driven Memory Access Tests

IEEE 1149.4 Update

New Boundary Scan I/O Modules enable structural Test of PCI Express Slots via IEEE Std. 1149.6

IEEE 1149.1 Introduction

One chain. Or two? Or more?

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